1. Field of the Invention
This invention relates to a vector summation device, more particularly to a vector summation device which generates an output voltage signal with a voltage value proportional to the square-root of the sum of the squares of the voltage values of a number of input voltage signals provided thereto.
2. Description of the Related Art
Presently, conventional vector summation devices usually employ a large number of bipolar junction transistors as its primary electrical components, thereby resulting in a complicated circuit. Furthermore, the conventional vector summation device is unsuitable for use in VLSI circuits.